(a) Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and more particularly, to a method of fabricating a copper line in a semiconductor device.
(b) Description of the Related Art
Tungsten (W), aluminum (Al), or an aluminum alloy are typically used as the metal to form a metal line in a semiconductor device. However, much research is being performed on ways to use copper (Cu) in place of tungsten and aluminum for the metal wiring in semiconductor devices because of the relatively low resistivity of copper and because copper provides for a high degree of reliability when used for such an application (i.e., the metal wiring in a semiconductor device).
Nevertheless, a drawback of copper is that, unlike with tungsten and aluminum, it is difficult to form lines in semiconductor devices by reactive ion etching. Accordingly, much research is being performed on ways to simultaneously form a plug and a line without the use of reactive ion etching. Such a process is referred to as a dual damascene process.
In the conventional dual damascene process in which copper is used, copper is blanket-deposited on a wafer, then unnecessary parts of the copper layer on a surface of the wafer are removed by chemical-mechanical polishing to thereby complete the formation of a copper plug and a metal line.
A conventional method for fabricating a semiconductor device will be described below with reference to FIGS. 1a through 1e. 
Referring first to FIG. 1a, a lower insulation layer 2 and a lower metal line 3 are formed on a semiconductor substrate 1. Next, a first SiC layer 4 for use as an etching completion layer during etching to form a via is formed over the lower insulation layer 2 and the lower metal line 3.
Following the formation of the first SiC layer 4, a first SiOC layer 5 is formed on the SiC layer 4. The SiOC layer 5 acts as an interlayer dielectric film. Formed over the first SiOC layer 5 is a second SiC layer 4′, which acts as an etching completion layer during etching to form a line opening. A second SiOC layer 5′ is formed over the second SiC layer 4′. The second SiOC layer 5′ acts as an interlayer dielectric film.
Next, with reference to FIG. 1b, a photosensitive layer is deposited on the second SiOC layer 5′, after which the photosensitive layer is exposed and developed to form a first photoresist pattern (not shown) for forming a line opening. Using the first photoresist pattern as a mask and the second SiC layer 4′ as an etching completion layer, the second SiOC layer 5′ and the second SiC layer 4′ are etched at a predetermined area to thereby form a line opening 100. The first photoresist pattern is then removed, after which a cleaning process is performed.
Subsequently, with reference to FIG. 1c, a second photoresist pattern (not shown) is formed on the second SiOC layer 5′. The second photoresist pattern has an opening centered about the line opening 100 and a width that is less than a width of an opening of the first photoresist pattern, that is, less than a width of the line opening 100. Using the second photoresist pattern as a mask and the first SiC layer 4 as an etching completion layer, the exposed first SiOC layer 5 and the first SiC layer 4 are etched until the lower metal line 3 is exposed to thereby form a via 200.
Next, with reference to FIG. 1d, a barrier metal layer 6 made of TaN is deposited to a thickness of approximately 300 Å over all exposed surfaces of the lower metal line 3, the first SiOC layer 5, and the second SiOC layer 5′. Next, a copper layer 7 is deposited on the barrier metal layer 6 until the via 200 and the line opening 100 are completely filled.
Referring to FIG. 1e, chemical-mechanical polishing is performed on the copper layer 7 until the second SiOC layer 5′ is exposed and the copper layer 7 is substantially flush with the same. As a result, the via 200 and the copper line layer are simultaneously formed.
However, in the configuration resulting from the conventional method described above, since the SiC layer 4′, which is used as an etching completion layer, is interposed between the SiOC layers 5 and 5′, which are interlayer insulating layers, the overall capacitance of the device is increased significantly when compared to when no SiC layer is formed between the SiOC layers 5 and 5′. This interferes with the free flow of current such that the operational speed of the device is reduced.
Further, with the direct contact of the photosensitive layers to surfaces and side walls of the SiOC layers for the formation of the line opening and the via, full removal of the photosensitive layers does not occur. This results in increasing the resistances of the via and the lie opening.